wafer.space Community - FlexMem Testing

3:11 a.m.

Any idea on a timeline when you might be able to do this? Keen to use the 32 bit macros

glaxus

Any idea on a timeline when you might be able to do this? Keen to use the 32 bit macros

If we're lucky I can draw up a suitable voltage supply (probably also acting as more-accurate-than-current ADC reference) add-on board for the bond tester's expansion header within about 100 hours from now; I'd then suggest we'd pack two of the 5 (if ordered min cheap quantity) along with a confirmed working bond tester and the suggested 2 bond-check-passed COBs of each of the 3 FlexMem dies together into a parcel and ship to Germany; I'm assuming the bond tester I'm offered is in China currently? Feel free to ask where it is/if it's there; I'd then try to get the programmable voltage supply for the low voltage testing that thus checks data resilience at "power save" sleep-supply-voltages (and indirectly confirms the array itself to be robust even if not directly qualifying a particular access speed) prepped at JLCPCB to conveniently get where the other bond testers are. Then the idea would be that I'd try to program it later next week/weekend-after-next, and once it's working for me someone who can be trusted enough to not break the gear or steal the parts could use one of the other bond testers with the add-on board and test a statistically significant quantity of those 150 FlexMem dies. To be clear, I'm not against doing that myself, but I don't currently have the resources to do much fancy beyond maybe putting a few DUTs with the board into a filament dryer offering concern at up to about 65C.

glaxus

Any idea on a timeline when you might be able to do this? Keen to use the 32 bit macros

If you'd want to help, a non-expensive 1% (ish) LDO that can do like 50 mA at outputs programmable from two digital RPiPico2 pins and voltages from at least like 3~3.4 ish Volts down to at LEAST 500 mV, ideally I'd want it down to about 300 mV. Ideally one that's stocked at JLCPCB, but worst case their ability to order from mouser/digikey at a unit price premium and handle the logistics for you would give that as an escape but I'd prefer not to, due to it being prone to delays. [Mostly I'm not sure if the SRAM control can behave itself enough at the very low voltage end; I'd probably expect most cells to retain even at very very low supply.]

4:19 a.m.

If you could find one, that'd accelerate things.

@Lauri you wrote this in src/hal/mux.cpp; does this mean it's currently suffering the slow behavior but could do the fast if one edits in a mythical (doesn't seem particularly specified here, but I'd guess it's imported/included from platformio?) header file? Because looking at the timing diagram in the datasheet we could let the falling clock coincide with the data transition. I know you don't need it to be very fast, due to your fairly high-Z measurements, but for the FlexMem testing I'd like to be at least somewhat near the MUX chip's potential speed.

// Speed note: replace digitalWrite with gpio_set_mask/gpio_clr_mask (hardware/gpio.h)
// for ~50x speedup (~200 ns/transaction vs ~10 µs). All CH446X setup/hold
// requirements (3–10 ns) are met by back-to-back SIO writes without added delays.

v1.1 tester you should be able to go faster. There's even PIO code for the sibling chip (CH446Q) https://discord.com/channels/1361349522684510449/1408134567491145728/1516311011437838427

Lauri

v1.1 tester you should be able to go faster. There's even PIO code for the sibling chip (CH446Q) https://discord.com/channels/1361349522684510449/1408134567491145728/1516311011437838427

Ohh ok good thx. Do you happen to know if the bond tester that's said to be tentatively scheduled to be sent to me (once I commit to teaching it FlexMem bitcell stress-testing) is in China? Would you consider the expansion header to be reasonable to put a programmable LDO on to support as here some testing at less than the 3.3V? Ofc it's inherently a limited architecture with the MUX but it could be so much worse

. And letting such simple checking be done by it should enable us to do much better testing for a bunch of chips even if it's somewhat awkward to pull off.

namibj

Ohh ok good thx. Do you happen to know if the bond tester that's said to be tentatively scheduled to be sent to me (once I commit to teaching it FlexMem bitcell stress-testing) is in China? Would you consider the expansion header to be reasonable to put a programmable LDO on to support as here some testing at less than the 3.3V? Ofc it's inherently a limited architecture with the MUX but it could be so much worse

. And letting such simple checking be done by it should enable us to do much better testing for a bunch of chips even if it's somewhat awkward to pull off.

Do you happen to know if the bond tester that's said to be tentatively scheduled to be sent to me (once I commit to teaching it FlexMem bitcell stress-testing) is in China?

yes.

Would you consider the expansion header to be reasonable to put a programmable LDO on to support as here some testing at less than the 3.3V?

Are you referring to the 7 pin J1 header? It has the signals you'd require, a power source, gpio's and one mux channel. You do need to remove the R12 pullup on this channel though. (I'm also assuming the mux Ron is not a problem for you?)

Lauri

Do you happen to know if the bond tester that's said to be tentatively scheduled to be sent to me (once I commit to teaching it FlexMem bitcell stress-testing) is in China?

yes.

Would you consider the expansion header to be reasonable to put a programmable LDO on to support as here some testing at less than the 3.3V?

Are you referring to the 7 pin J1 header? It has the signals you'd require, a power source, gpio's and one mux channel. You do need to remove the R12 pullup on this channel though. (I'm also assuming the mux Ron is not a problem for you?)

Really shouldn't be a problem; I primarily care about voltage at static holding below 1.5V VDDD.

I've figured out a way to do programmable LDO with commodity parts: a 12 bit I2C DAC and an "adjustable"-style LDO, and a 3-resistor weighted summer mixing Vout/GND/Vdac at the LDO's FB node. Should easily give about 1mV steps from around 50 mV to around 3.2-ish V. Well, technically Gemini did the looking for me but I'm pretty sure those parts are actually commodity (or very similar ones at least). I wasn't planning on deleting the pull-up but rather adding a preload to GND to overpower R12 and give the LDO some nicer operating conditions. I'll try to get a layout on Wednesday; if there's no plan yet regarding what kind of header that is, may I request that to be decreed by then to allow including a matching connector and board orientation to go with it? Any preference about I2C assignment to the two GPIOs on the header? I'd put one of them simple EEPROMs on it I guess... Should I provide precise 3.3V on it as well or would that be counter-productive due to how invasive the changes to the tester board would be for custom 3v3 supply? I could probably go for just calibrating the ADC by muxing COMA and COME together, I'd hope the existing 3v3 reference doesn't drift wildly within a minute or so at least...

namibj

I've figured out a way to do programmable LDO with commodity parts: a 12 bit I2C DAC and an "adjustable"-style LDO, and a 3-resistor weighted summer mixing Vout/GND/Vdac at the LDO's FB node. Should easily give about 1mV steps from around 50 mV to around 3.2-ish V. Well, technically Gemini did the looking for me but I'm pretty sure those parts are actually commodity (or very similar ones at least). I wasn't planning on deleting the pull-up but rather adding a preload to GND to overpower R12 and give the LDO some nicer operating conditions. I'll try to get a layout on Wednesday; if there's no plan yet regarding what kind of header that is, may I request that to be decreed by then to allow including a matching connector and board orientation to go with it? Any preference about I2C assignment to the two GPIOs on the header? I'd put one of them simple EEPROMs on it I guess... Should I provide precise 3.3V on it as well or would that be counter-productive due to how invasive the changes to the tester board would be for custom 3v3 supply? I could probably go for just calibrating the ADC by muxing COMA and COME together, I'd hope the existing 3v3 reference doesn't drift wildly within a minute or so at least...

I'll try to get a layout on Wednesday; if there's no plan yet regarding what kind of header that is, may I request that to be decreed by then to allow including a matching connector and board orientation to go with it?

Tester boards have the J1 part unpopulated. You can choose the connector you like.

I also could not find an LDO that fit those parameters. I wonder if a DAC + voltage follower + pass fet would work

glaxus

I also could not find an LDO that fit those parameters. I wonder if a DAC + voltage follower + pass fet would work

well the idea so far was as mentioned a DAC giving an additive offset to the feedback voltage as applied to the fb pin of an adjustable LDO. Because in essence those are just op-amps with single ended output and the positive input hard-tied to whatever reference voltage they are specified to.

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@Tim 'mithro' Ansell Stuart Said to ask you for approval first. I'd like to draw up a simple add-on board tomorrow with an I2C DAC, an I2C serial/eeprom/-style chip (for calibration and/or such), an adjustable LDO, 3 resistors summing these together to create a programmable LDO from it, and probably a somewhat decent (at least in drift over time and temperature) voltage reference for the LDO and the I2C DAC. I'd prefer to get JLC to assemble a pack of 5 and ship them to where the bond testers are; I'd request two of them for me to be bundled with the tester and (assuming they'd conveniently meet the COBs) 2 of each FlexMem COB; I'd be willing to donate the rest of the assembled "programmable LDO" tester-add-on modules. Once I have a system quote from JLC (needs the board to pass their automated DRC) we could discuss if you'd want to order from them or if I'd order it shipped to you or what (whichever you'd like, I don't need a decision before I'm ready to place the order anyways). I'd expect it to be like 25$ or such for the 5-pack anyways.

@namibj

A few thoughts....

(1) I would like to try and use NextPCB a little bit more, they are working with CrowdSupply and us around trying to make accessible CoB happening and I would like to reward that if it doesn't cost me too much.

(2) I'd happily drop $25 USD on something like this - I would probably do a 10-pack if other people think it is usable.

(3) The more concern would be if @Lauri / @stuart would need to charge me for work hours. They are a bit more expensive than the board.

(4) This is probably not something we would be using / doing in the factory.

(5) We could probably put these items into shipment to people like @Chips4Makers aka Staf Verhaegen / @Tim Edwards / @Essen / etc when we ship them silicon.

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2

@Tim 'mithro' Ansell re: (3) no worries there, happy to help @namibj the testers should be ready to ship this week or early next week. If we wait for your addons to arrive first, your shipment will likely be delayed by few weeks. If you're happy to proceed then I can DM you the shipping address later

I can see about nextpcb if you want. I'll try to get things done though. And yeah, I'm happy to proceed. Keep in mind the tester without the FlexMem COB is of limited utility to me (I could at most start calibrating the programmable LDO setup). And yeah I understand it's likely not factory stuff, it's more that I don't want to take possession of a statistically significant quantity of FlexMem dies from the first batch of wafers, leaving that to ideally someone who will have them anyways and would have time to cycle them through after I've finished the firmware for it.

Lauri

@Tim 'mithro' Ansell re: (3) no worries there, happy to help @namibj the testers should be ready to ship this week or early next week. If we wait for your addons to arrive first, your shipment will likely be delayed by few weeks. If you're happy to proceed then I can DM you the shipping address later

Yeah I'll take the 1-2 week of delay.

1

Lauri

@Tim 'mithro' Ansell re: (3) no worries there, happy to help @namibj the testers should be ready to ship this week or early next week. If we wait for your addons to arrive first, your shipment will likely be delayed by few weeks. If you're happy to proceed then I can DM you the shipping address later

As you said "no worries there, happy to help", can I request a judgement as to what kind of connector situation to go for with the still-unpopulated header on the tester mainboard, to then connect to the add-on board? It's looking to be just a tiny add-on board; I'm now actually thinking to use an op-amp from the 5V feed to buffer https://jlcpcb.com/partdetail/MicrochipTech-MCP4725A0T_ECH/C144198 given that I don't actually need the true LDO behavior I kinda was going for until a few minutes ago.

MCP4725A0T-E/CH | Microchip Tech | JLCPCB

MCP4725A0T-E/CH - -40℃~+125℃ 1 12 2.7V~5.5V 210uA 2LSB 6us I2C Integrated buffer、Power-on reset、Power-down mode Voltage Buffer SOT-23-6 Digital to Analog Converters (DAC) ROHS. Check prices, specs, datasheet, and order now!

I'm thinking to put a right angle male header on the top facing inwards (not extending outside the mainboard PCB) and a female right angle header on the bottom of the add-on board so they fit "over" the wafer.space logo.

4:16 a.m.

Or, given this "assembled" geometry with the DUT adapter and an actual DUT present, maybe just have a regular vertical male header on the main board and a regular vertical female header on the add-on stacked above (with the PCB "planes" parallel to another and the add-on living conveninetly over top the mainboard, in the same area but not as low-profile as the right-angle solution would have been).

Tim 'mithro' Ansell

@namibj

A few thoughts....

(1) I would like to try and use NextPCB a little bit more, they are working with CrowdSupply and us around trying to make accessible CoB happening and I would like to reward that if it doesn't cost me too much.

(2) I'd happily drop $25 USD on something like this - I would probably do a 10-pack if other people think it is usable.

(3) The more concern would be if @Lauri / @stuart would need to charge me for work hours. They are a bit more expensive than the board.

(4) This is probably not something we would be using / doing in the factory.

(5) We could probably put these items into shipment to people like @Chips4Makers aka Staf Verhaegen / @Tim Edwards / @Essen / etc when we ship them silicon.

10 boards, assembled, except for an optional single pin header that could be tied to the Pi Pico2's ADC_REF pin (floating on r2 tester board) via, as far as my plan goes, adding a single male header to both the Pi Pico 2 and the otherwise unpopulated side of the add-on board and connecting them via a jumper. They'are decoupled on both ends so I'm not too worried about it picking up EMI at least. That works via the suggested 3.0V shunt regulator that one can add there; it's otherwise used to regulate the DAC; there's also a strong buffer that should at least keep the COME side of the net on the mainboard close to the programmed voltage. There is no modification to the main board suggested other than adding the two pin headers (the expansion header and a lone one directly to the ADC_REF pin).

As you said "no worries there, happy to help", can I request a judgement as to what kind of connector situation to go for with the still-unpopulated header on the tester mainboard, to then connect to the add-on board?

Generally my first preference is for the powered side to have a female connector to guard against accidental shorting. But I think your suggestion of right angle (male) is also fine because this keep the tester compact and the addon board wouldn't be in the way. (edited)

Lauri

As you said "no worries there, happy to help", can I request a judgement as to what kind of connector situation to go for with the still-unpopulated header on the tester mainboard, to then connect to the add-on board?

Generally my first preference is for the powered side to have a female connector to guard against accidental shorting. But I think your suggestion of right angle (male) is also fine because this keep the tester compact and the addon board wouldn't be in the way. (edited)

oh ok; I've selected the reverse as I think I mentioned, motivated by that the female side tends to be the wear item and I don't want to turn the mainboard into a wear item. Let me know if I have to swap that.

10:22 a.m.

namibj

Click to see attachment 🖼️

full contents with PCB and such

ProPrj_BondTest72_MCP4725_ADC_add-on_r1_2026-10-23.epro

82.1 KB

10:23 a.m.

(iirc kicad imports that without complaints, but they iirc have a web version of their editor as well)

you don't have to swap it.

the Pi itself also has that 200 Ohm into 2.2uF to get it's ADC_REF from it's +3.3V; having that LM4040xxx-3.0 to pull that down to a stable 3.0V is explicitly suggested/recommended to do for a stable reference. The Op amp is a type that's safe for even large capacitive loads and it's offset exists but shouldn't be drifting enough for that to dominate.

10:27 a.m.

If this looks good enough so far, I'd finish eating and probably just click it (if I have the address on hand?)

I'd suggest adding pullups to i2c signals

Lauri

I'd suggest adding pullups to i2c signals

how high is acceptable?

10:42 a.m.

(this isn't fast)

namibj

how high is acceptable?

I'd add 4.7k just in case to avoid any E9 related problems. These picos should be rev A2.

Tim 'mithro' Ansell

@namibj

A few thoughts....

(1) I would like to try and use NextPCB a little bit more, they are working with CrowdSupply and us around trying to make accessible CoB happening and I would like to reward that if it doesn't cost me too much.

(2) I'd happily drop $25 USD on something like this - I would probably do a 10-pack if other people think it is usable.

(3) The more concern would be if @Lauri / @stuart would need to charge me for work hours. They are a bit more expensive than the board.

(4) This is probably not something we would be using / doing in the factory.

(5) We could probably put these items into shipment to people like @Chips4Makers aka Staf Verhaegen / @Tim Edwards / @Essen / etc when we ship them silicon.

I can also bear some extra costs for testing equipment. For me, main problem at the moment is lack of time to dive into the testing procedure and setup.

Chips4Makers aka Staf Verhaegen

I can also bear some extra costs for testing equipment. For me, main problem at the moment is lack of time to dive into the testing procedure and setup.

Quick question, can you confirm that for testing at around 1 MHz access speed, all 3 of your FlexMem dies are expected to be happy with just 10~30 mA of current, other than what the on-COB decoupling capacitors will cover? I'll suggest you can cover the labor of running more than 2 of each FlexMem test chip through the machine once I've programmed it. And/or can perhaps help me with the FC01 flip-chip bonding tests (some flex pcbs for their very fine pitch and see-through-ness that gives easy visual alignment; suitable ACF tape; what's needed to decently-reliably perform the hot press action in a way that ought to be repeatable/transfer-to-other-dies (not complicated, but probably a die-size "heated anvil" based on I'd guess approximately the same technology as a 3D printer hotend).

10-30mA should be plenty of power for the SRAMs. It does not include power for the output pins though as that depends on the capacitive load on these outputs.

Chips4Makers aka Staf Verhaegen

10-30mA should be plenty of power for the SRAMs. It does not include power for the output pins though as that depends on the capacitive load on these outputs.

yeah I know they aren't a problem though because those transients are just absorbed and I can make them happen slow enough if the current would be too high.

4:59 a.m.

(I probably put the output pins as high-Z as the analog mux gets as far as I can, mostly due to just not having spare pins on the PiPico2 side of the mux.)

So, I just accidentally read doi:10.1109/jssc.2019.2963002, having gotten distracted by curiosity as to WTH they mean with nmos-only "SRAM PUF bitcells" (like, what the schematic is and why they're doing it; see attached schematic if curious and know the high seas have this specific paper at the very conveniently accessible place (thanks to it being released and people caring about it prior to the convenient place ceasing acceptance of new papers)), and it said:

Compared with a conventional CMOS SRAM, whose transition voltage is below 0.1 V, the transition voltage of an EE SRAM bit cell is in the super-threshold region, and hence, the transistors have higher conductivity.

(emphasis mine) So, welp, I guess I may have accidentally mis-aligned the add-on-board's target voltage zone of particular voltage accuracy, having had assumed the relevant voltages to be more around the 500~1000 mV range (approximately). Brief further googling corroborates that "roughly 100 mV" for the approximately 90~350 nm process node families we've been looking at with the open PDK and related/derivative MPW efforts (e.g. counting in the indian and the japanese old-node MPW announcements and PDK reveals (though the indian might still have the PDK natinality/export controlled? and the japanese one was iirc actually a 500nm process and therefore really bad for digital SCL designs, and IMO pure analog stuff is quite legacy by now at least for application tasks that would somewhat reasonably warrant a custom 500nm CMOS ASIC, as it can't be anything fast or efficient and slow inefficcient ASICs tend to target accuracy specs that would reasonably require per-die trimming to mitigate process mismatch, and doing such very trimming through DAC structures is far more accessible than laser trimming (no need for pre-packaging analog characterization of each die to employ that very laser trimming while the trimmable structures are still accessible to a laser), given that we e.g. have very tested functional polyfuse cells (at least with 5/6V programming instead of attempting programming at just 3.3V) on gf180mcuD (and AFAIK had already on sky130A and I think also had on IHPSG13).....) ....at least https://mediatum.ub.tum.de/doc/1084703/1084703.pdf suggests in section 5.4.2 that triggering read conditions for a wordline while the supply voltage of the SRAM core array (not the periphery with decoders and amplifiers and multiplexers, just the bitcell VDD) is dropped, at least if it's possible to force the WL to stay active for several milliseconds, would provide effective measurements of read margin. It's not perfect but I guess the wisdom from that dissertation (notably I'll point out it's convenient collation of applicable methodologies and their comparative nuances) should help in using the FlexMem test dies from Run2 to gather statistically significant information on bitcell behavior and specifically how those distributions actually look; if we're lucky "muxed e-test" happens on Run3 and we could drop some sense amplifiers and bitcells (at least if feasible given the array nature of repeating patterns affecting lithography if we try to PnR a lone one to wire it up to the mux to do DC-conditions e-tests on the bitcell), which should be effective for translating the then already collected statistical measurements from the FlexMem Run2 dies into practical-user-of-FlexMem-applicable-performance-numbers. I kinda now just hope that read states can be held with the limitations given by the sequencer machinery of the periphery on those Run2 dies (I admit I haven't yet looked at those detailed enough to know this from memory). Let's just hope that the decoupling capacitors can genuinely effectively decouple VDD transients of accesses if I orchestrate the tester to insert sufficient delays into the sequencer/testing patterns, to allow proper read and write access stress-testing across temperatures and voltages up-to-3.0V.

1084703.pdf

4.53 MB

1:14 p.m.

(Plain access testing at 3.3V from the PiPico2 supply, with the DAC add-on board removed, is also easily possible (likely would involve a single jumper plugged into the expansion header in place of the add-on board though to have a low-impedance 3.3V supply to the DUT, with on the order of 50 Ohm PDN resistance instead of the tester's native (r2 at least), and unless I mixed up the exact value 1k Ohm). Testing the thick oxide FlexMem die at supply voltages in excess of 3.3V will not be nearly as easy, as the tester hardware I'm piggybacking on won't handle that with it's ADC hardware and I've therefore skipped targeting support for such VDD supplies. .....swapping the PiPico2 for something like an analog discovery and adjusting the VDD supply infrastructure and I guess putting a 5/6V reference on the add-on board (or using the analog discovery type thingy to DAC such a voltage with acceptable accuracy) might allow re-using much of the test pattern/orchestration code, by basically swapping the HAL and porting what differences remain?) (edited)

Tim 'mithro' Ansell

@namibj

A few thoughts....

(1) I would like to try and use NextPCB a little bit more, they are working with CrowdSupply and us around trying to make accessible CoB happening and I would like to reward that if it doesn't cost me too much.

(2) I'd happily drop $25 USD on something like this - I would probably do a 10-pack if other people think it is usable.

(3) The more concern would be if @Lauri / @stuart would need to charge me for work hours. They are a bit more expensive than the board.

(4) This is probably not something we would be using / doing in the factory.

(5) We could probably put these items into shipment to people like @Chips4Makers aka Staf Verhaegen / @Tim Edwards / @Essen / etc when we ship them silicon.

I quoted NextPCB's auto-quote rev0 PCBA just to see if they'd have been less expensive or such, and.... well, with the one time use 500$ off (rev0 assembly only, doesn't discount the PCB production part or the component sourcing), it would have been 94ct (USD currency, i.e., just under 1 USD) more expensive than JLC was, and that's not counting shipping costs (which were 2.07 USD at JLC). I'll try to make sure to quote them next time I'd go for a big "fancy" order that's of a kind/nature that isn't cheap at JLC. Opinion/attempted explanation for massive pricing difference: The core issue seems to be lack of economically handling the boards as multi-customer panels until after assembly, not having a streamlined common-parts pick-and-place line set up that allowed 4 of the 8 parts at JLC to be picked from pre-setup feeders (instead of necessitating rolling in a shelf reel into a fresh feeder) at no per-bom-line cost as well as not having to set up the pick-and-place machines for any customer-specific panel size/fiducials.